Integrated semiconductor memory device
US6560149B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Feb 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/787
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.