System and method for power saving memory refresh for dynamic random access memory devices after an extended interval
US6560155B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay device is added to the addressing and refreshing circuitry of a DRAM array comprised of DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals generated by a conventional DRAM refresh controller and initiates a refresh cycle after disregarding a predetermined number of refresh signals generated by the refresh controller whose total duration equals the interval by which the less volatile DRAM devices must be refreshed. The delay device also is adapted to power off circuitry needed to address the DRAM devices when the DRAM devices are not being refreshed or otherwise accessed. Additional circuitry is added to selectively power on only specific addressing devices actually needed to address those certain portions of the array being refreshed at that time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.