Data receiver that performs synchronous data transfer with reference to memory module
US6560661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0996
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal receiving system includes a plurality of first receivers and at least one second receiver driven based on a sensing result output from the first receivers, the first receivers driven at predetermined time intervals and sensing a time-based change in a first signal. Each of the first receivers holds the first signal with a predetermined time difference and thereby converts the time-based change in the first signal into positional information. The signal receiving system may also include a clock generation section that generates clock signals that are different in phase. The signal receiving system is provided with an S receiver and a D receiver. The S receiver is driven on the basis of first multiphase clocks and receives strobe signals. The D receiver is driven on the basis of outputs from the S receiver that receives states of the strobe signals at the respective times and second multiphase clocks, which lag the first multiphase clocks by a predetermined length of time. The D receiver receives data and transfers the same. The receivers may be incorporated in a controller which receives data from memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.