Handling contiguous memory references in a multi-queue system
US6560667B1 · kind B1 · utility
75Cited by
8References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references, such that the arbiter services a same queue until the chaining bit is cleared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.