System and method for terminating lock-step sequences in a multiprocessor system
US6560682B1 · kind B1 · utility
12Cited by
24References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1997 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.