Soft error detection for digital signal processors
US6560733B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1999 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jul 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides an initialization routine for digital signal processors that detects and maps out soft errors. A digital signal processing system may include an initialization routine stored in a non-volatile memory device that writes a bit pattern to the memory arrays. The routine may then cause the processor to perform refresh cycles to refresh the charge of each bit in the arrays. Next, the initialization routine may read data values from the memory arrays and compare them with the previously written bit pattern. If a value does not match the bit pattern, then the bit may have failed due to a soft error. An indication of the failed bit may then be stored in the first few rows of the memory array, thereby mapping out the failed location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.