Cavity down flip chip BGA
US6562656B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Oct 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The process of the invention starts with a metal panel, overlying the metal panel is created an interconnect substrate making use of BUM and thin film processing technology while the process of the invention enables the use of stacked vias and merged vias for the connection of the flip chip bumps. The process of the invention creates, for instance, two patterned layers on the surface of the metal panel whereby the metal panel is used as the ground terminal of the power supply. The first layer that is created on the surface of the metal panel can be the power supply layer (this layer can also be used for some fan-out interconnect lines), the second layer that is created on the surface of the metal panel is primarily used for (fan-out) interconnect lines. The flip chip bumps are, under the process of the invention, connected to the second layer of the interconnect substrate. Where the BGA balls also reside on the same surface as the flip chip bumps, the process of the invention does not require any additional structures such as a dam for the containment of insulating encapsulation material (underfill) that at times is provided around a perimeter of a well into which a flip chip is in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.