System carrier for a semiconductor chip having a lead frame
US6563201B1 · kind B1 · utility
8Cited by
10References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system substrate for a semiconductor chip has a conductor frame (1); many small-area signal flat conductors (4) extend from webs (2, 3) of the conductor frame and on their free ends have contact terminal faces (5). Remaining faces (6) between the webs (2, 3) and the many signal flat conductors (4) are occupied by large-area flat conductors (7). Between the large-area flat conductors (7) and the webs (2, 3), there are connecting webs (9) with bent areas (8) at various spacings from the webs (2, 3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.