Probe card and method of testing wafer having a plurality of semiconductor devices
US6563330B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/326
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. Displacements of the internal terminal resulting from the temperature load applied during testing of the wafer are compensated by the level transitioning portion of the first wiring. Une…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.