Low power static RAM architecture
US6563730B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Apr 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static RAM bit cell and a system and method for operating an array of such static RAM bit cells. The static RAM bit cell herein includes a cell of four transistors configured to store data. It also includes a pair of word line pass transistors and a pair of column pass transistors coupled to the cell of four transistors. The word line pass transistors are coupled to a word line such that they can be opened in closed in response to a signal on the word line. The column pass transistors are coupled to a column select transistor such that they can be opened and closed in response to a signal on the column select line. Using this configuration signals can be generated on the word line and the column select line so that only a small fraction of the total number of static RAM bit cells in an array need to be charged and discharged in connection with performing read and write operations to a specific static RAM bit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.