Semiconductor memory device
US6563755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Nov 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to read or write stored information or information to be stored and a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation before or after such first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells are not mutually affected in the first memory operation and the second memory operation or the refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.