Method and apparatus for timing driven resynthesis
US6564361B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | May 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises method for optimizing an integrated circuit design that includes computing of capacities and delays of an integrated circuit design, resynthesizing said integrated circuit design utilizing a plurality of local optimization procedures, and removing overlap the local optimization procedures can include a local resynthesis of logic trees procedure that utilizes multiple cost functions, a dynamic buffer and inverter tree optimization procedure, and a cell resizing procedure. Generally, faster local optimization procedures are applied first and slower, more thorough procedures are applied to areas where the faster procedures have not solved the optimization tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.