Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices
US6566190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Aug 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.