Method of forming an insulating layer in a trench isolation type semiconductor device
US6566229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Nov 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.