Method of manufacturing high performance semiconductor device with reduced lattice defects in the active region
US6566231B2 · kind B2 · utility
31Cited by
4References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 23, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Mar 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02647
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first semiconductor layer is epitaxially grown on a semiconductor substrate and patterned to form concave and convex portions. A second semiconductor layer is formed on the first semiconductor layer using a top epitaxial mask covering the top surface of the convex portion. Lattice defects D propagating from the first semiconductor layer exist only in a region located above the center of the concave portion (a defect region Ra), while in the other region (a low defect region Rb) lattice defects D propagating from the first semiconductor layer hardly exist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.