Semiconductor device manufacturing method having a step of forming a post terminal on a wiring by electroless plating
US6566239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | May 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a wiring layer on an underlying metal film formed on a substrate, the wiring layer being electrically connected to an electrode pad formed on a substrate, removing a part of the wiring layer so as to form a wiring on the substrate, a part of the underlying metal film being exposed other than a part where the wiring is formed, removing the exposed part of the underlying metal film by using the wiring as a mask, forming a barrier metal film on the wiring so as to cover the wiring and the underlying metal film underneath the wiring, forming a post terminal by electroless plating so that the post terminal is electrically connected to said wiring and providing a sealing resin so as to cover said substrate except a position at which said post terminal is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.