Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
US6566704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.