Semiconductor die package with improved thermal and electrical performance
US6566749B1 · kind B1 · utility
84Cited by
15References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2002 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.