Current crowding reduction technique for flip chip package technology
US6566758B1 · kind B1 · utility
6Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Nov 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.