Parallel push algorithm detecting constraints to minimize clock skew
US6566924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2001 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.