Single level metal memory cell using chalcogenide cladding
US6567293B1 · kind B1 · utility
387Cited by
14References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Nov 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.