Method and apparatus for a 5:2 carry-save-adder (CSA)
US6567835B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3872
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T0, T1, and T2. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.