Invention to allow hierarchical logical-to-physical checking on chips
US6567958B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Feb 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Layout cells having the same name as a corresponding schematic are checked hierarchically, with a single instance of a particular layout cell being checked internally for compliance with design rules and the like while remaining instances are merely checked for proper connection to neighboring cells. Layout cells which are not named the same as any schematic are automatically exploded for flat checking at the transistor level. Thus hierarchical checking is preserved for those layout cell instances named for the corresponding schematic, which should be the large majority of cell instances in any given integrated circuit, while cell instances meeting special layout requirements, which should be a small number of cases, are supported for any given schematic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.