Wafer scale integration and remoted subsystems using opto-electronic transceivers
US6567963B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2000 |
| Grant date | May 20, 2003 |
| Priority date | — |
| Expiry date | Mar 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4249
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An apparatus and method for optically interconnecting subsystems of a microprocessor system, whether co-located on a common wafer or divided among two or more wafers or substrates. Photo- transceiver arrays adjacent all or selected subsystems are optically interconnected to other subsystems for data transfer, enabled by protocol embedded in the CMOS circuitry in the respective substrates, enabling high speed and large bandwidth communications. Subsystems on a wafer can be located at some distance apart and communicate via the optical interconnect without adverse propagation delays. In a preferred embodiment a central processing unit (CPU) interfaces optically with a plurality of remote memory or co-processor subsystems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.