Method of manufacturing MOS transistor with fluoride implantation on silicon nitride etching stop layer
US6569726B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2002 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | May 22, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/919
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013 ˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.