Semiconductor device
US6570206B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Sep 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.