Circuit configuration for quantization of digital signals and for filtering quantization noise
US6570512B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Aug 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3022
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter. In an adder, said quantized output signals are then added to the first quantized output signal of the first digital control loop of the series to prevent quantization errors. The output signal of the adder has a second word length of n-bits and represents the quantized output signal of the circuit configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.