Semiconductor memory having refresh function
US6570801B2 · kind B2 · utility
9Cited by
6References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.