Adaptive equalization circuit and method
US6570916B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1997 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Mar 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing based adaptive equalization circuit (10) dynamically monitors a signal received at an input terminal (16) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit (26) centers the transition of the equalized signal in a delay line circuit (31). An analog delay locked loop circuit (29) provides a fixed throughput time for matching delay elements of delay line circuits (31, 41 and 51) in the adaptive equalization circuit (10). Timing signals propagating in the delay line circuits (31, 41 and 51) are stored in sampler circuits (36, 46 and 56). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits (46 and 56).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.