Phase lock loop having a robust bandwidth and a calibration method thereof
US6570947B1 · kind B1 · utility
7Cited by
25References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Sep 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref=(Fmin+Fmax)/2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.