Noise-tolerant digital adder circuit and method
US6571269B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital adder circuit is implemented using a Kogge-Stone architecture. Various embodiments utilize single-ended domino circuits, to which are input single-ended primary addends. Dual-function generator circuits generate differential sum and sum-complement output signals. The use of low VT devices and full CMOS circuitry provides a relatively high degree of noise immunity. Also described are a microprocessor having an ALU incorporating one or more of the adder circuits, as well as a method of adding two numbers which generates differential sum and sum-complement outputs but does not use full-differential domino circuits, thus providing considerable savings in circuit area, circuit conductors, and layout complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.