Single event upset tolerant microprocessor architecture
US6571363B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | May 27, 2003 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two passes through a block of instructions. A match of signatures generated from the two passes through the block of instructions indicates valid operations, a mismatch indicates an error. A software assisted solution compares a signature generated from one pass through a block of instructions with a signature pre-calculated by a compiler or with a one of a set of pre-calculated signature selected at run time. This is useful for digital signal processor design using deep-sub-micron devices and dynamic logic for superior system performance by enabling detection of errors that can result from the low noise-immunity in circuits using higher impedance smaller devices with low threshold voltage and dynamic logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.