Simulator-independent system-on-chip verification methodology

US6571373B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert J. Devins · South Burlington, US
• Mark E. Kautzman · Colchester, US
• Kenneth A. Mahler · Cincinnati, US
• William E. Mitchell

Key dates

• Filing date: Jan 31, 2000
• Grant date: May 27, 2003
• Expiry date: Jan 31, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/33
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for communicating with and controlling design logic modules (“cores”) external to a system-on-chip (SOC) design during verification of the design uses verification software to generate and apply test cases to stimulate components of an SOC design in simulation; the results are observed and used to de-bug the design. Typically, SOC designs interface with cores that are external to the design. Existing methods of including such external cores in a verification test of a SOC design typically entail having to create special test cases to control the external cores; such test cases typically do not communicate with test cases being applied internally to the SOC and therefore lack realism. An external memory-mapped test device (EMMTD) according to the present invention is coupled between a SOC design being tested in simulation, and cores external to the SOC design. Internal EMMTD logic provides for control and status monitoring of an external core coupled to an EMMTD bi-directional bus by enabling functions including driving data on the bus, reading the current state of data on the bus, and capturing positive and negative edge transitions on the bus. In one embodimen…