Method of forming spacers in CMOS devices
US6573133B2 · kind B2 · utility
2Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | May 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02271
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sidewall spacer is formed in a CMOS device by depositing a layer of silicon nitride on a wafer and anisotropically etching away the silicon nitride layer with a chorine-based plasma etchant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.