Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device
US6573170B2 · kind B2 · utility
18Cited by
9References
12Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 27, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Dec 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device including a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.