Atsushi Ogishima
19Patents
9h-index
45Co-inventors
68Inventor score
Filing activity: May 7, 1992 → Aug 18, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6503794B1 | Semiconductor integrated circuit device and method for manufacturing the same | Emerging Cross-Sectional Technologies | 66 | Expired |
| US6762449B2 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE PROCESS OF MANUFACTURING THE SAME HAVING POLY-SILICON PLUG, WIRING TRENCHES AND BIT LINES FORMED IN THE WIRING TRENCHES HAVING A WIDTH FINER THAN A PREDETERMINED SIZE | Electricity | 64 | Expired |
| US6743673B2 | Semiconductor integrated circuitry and method for manufacturing the circuitry | Emerging Cross-Sectional Technologies | 49 | Expired |
| US5734188A | Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same | Electricity | 37 | Expired |
| US5917211A | Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same | Electricity | 21 | Expired |
| US5264712A | Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same | Electricity | 21 | Expired |
| US6573170B2 | Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device | Electricity | 18 | Expired |
| US6287914A | Method of forming a MISFET device with a bit line completely surrounded by dielectric | Electricity | 11 | Expired |
| US6734479B1 | Semiconductor integrated circuit device and the method of producing the same | Electricity | 10 | Expired |
| US6562695B1 | Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing | Electricity | 6 | Expired |
| US6204184A | Method of manufacturing semiconductor devices | Electricity | 6 | Expired |
| US6867092B2 | Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size | Electricity | 6 | Expired |
| US7026679B2 | Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size | Electricity | 3 | Expired |
| US7081649B2 | Semiconductor integrated circuitry and method for manufacturing the circuitry | Emerging Cross-Sectional Technologies | 3 | Expired |
| US6800888B2 | Semiconductor integrated circuitry and method for manufacturing the circuitry | Emerging Cross-Sectional Technologies | 2 | Expired |
| US6720234B2 | Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing | Electricity | 2 | Expired |
| US6498100B2 | Method of manufacturing semiconductor devices | Electricity | 0 | Expired |
| US7397104B2 | Semiconductor integrated circuit device and a method of manufacturing the same | Electricity | 0 | Expired |
| US6380085B2 | Method of manufacturing semiconductor devices | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.