Method of forming dual damascene structure
US6573187B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 1999 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method is provided for creating a dual damascene structure. Two layers of dielectric are deposited in sequence. The lower layer of dielectric is the via dielectric and is selected such that it has a low etching rate (when compared with the upper layer of dielectric) and results in different volatile gas during the etch of the via. A first photoresist is patterned for the via, the etch for the via etches through both layers of dielectric. A second layer of photoresist is patterned for the trench etch, due to the difference in etch rate between the two layers of dielectric, the trench of the dual damascene structure is etched without further affecting the via etch in the lower layer of dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.