Post in ring interconnect using for 3-D stacking
US6573460B2 · kind B2 · utility
7Cited by
74References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A post in ring interconnect used for 3-D stacking. A retaining ring is formed on a pad on a bottom surface of a top PCB substrate to be stacked with a bottom PCB substrate. A post is formed on a pad on a top surface of the bottom PCB substrate. A conductive paste is applied on the pad on the bottom surface of the top PCB substrate and retained in a pocket partially defined by the retaining ring. The retaining ring is aligned with the post. By performing a compression step, a eutectic bond is formed between the top and bottom PCB substrates by the post and the conductive paste.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.