Dynamic threshold voltage 6T SRAM cell
US6573549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2002 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jun 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/125
Abstract
An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the first transistor; and a second transistor (130 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of the second transistor and the current path of the first transistor, the current path of the second transistor connected to the backgate/body connection of the first transistor; an input/output conductor; and a pass transistor coupling the memory cell to the input/output conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.