Input-output buffer circuit and method for avoiding inadvertent conduction of a pull-up transistor
US6573765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Nov 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input-output (I/O) buffer and a method of biasing an I/O buffer that avoids inadvertent conduction of a pull-up transistor included in the buffer when an input signal having a voltage greater than the supply voltage is applied to the I/O buffer in an input mode. Inadvertent conduction of the pull-up transistor is avoided during an input mode by biasing the gate and the body of the pull-up transistor with a supply voltage until the voltage of the input signal exceeds the voltage of the voltage supply, at which time the voltage of the input signal is applied to the gate and the body of the pull-up transistor instead. The I/O buffer includes a driver circuit having a pull-up transistor and an I/O node to receive an input signal. The I/O buffer also includes a pull-up transistor bias circuit to provide the voltage to the gate and the body of the pull-up transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.