Circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits
US6574132B2 · kind B2 · utility
1Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jul 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a circuit configuration for equalizing different voltages on line runs in integrated semiconductor circuits, where the bit line and the plate line have a voltage equalization transistor provided between them which, in normal operation of the semiconductor circuit, can be switched to low impedance by a control signal in order to equalize the different voltages on the lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.