Differential redundancy multiplexor for flash memory devices
US6574141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for a differential redundancy multiplexor for flash memory devices. One embodiment comprises a memory array comprising a main memory element and a redundant element. A sense amp is coupled to the memory array to evaluate the main memory element and to generate a first pair of differential output signals. A redundant sense amp is coupled to the memory array. The redundant sense amp is to evaluate the redundant memory element and to generate a second pair of differential output signals. A multiplexor is coupled to the sense amp and the redundant sense amp. The multiplexor is to receive the first pair and the second pair. The multiplexor is to generate a single ended output from evaluating a single pair of differential output signals. Control logic coupled to the multiplexor to control whether the first pair or the second pair is the single pair of differential output signals evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.