Heuristic for identifying loads guaranteed to hit in processor cache
US6574713B1 · kind B1 · utility
13Cited by
9References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2000 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Mar 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heuristic algorithm which identifies loads guaranteed to hit the processor cache which further provides a “minimal” set of prefetches which are scheduled/inserted during compilation of a program is disclosed. The heuristic algorithm of the present invention utilizes the concept of a “cache line” (i.e., the data chunks received during memory operations) in conjunction with the concept of “related” memory operations for determining which prefetches are unnecessary for related memory operations; thus, generating a minimal number of prefetches for related memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.