Hierarchical layout method for integrated circuits
US6574779B2 · kind B2 · utility
48Cited by
22References
28Claims
0Family size
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Key dates
| Filing date | Apr 12, 2001 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Jul 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for hierarchical layout of an electronic design using an electronic computer aided design system, wherein the method includes generating a parameterized pattern library and using an existing netlist and analyze in a pattern recognizer, from which a list of associations between the pattern library and the netlist is created. Renesting then occurs wherein the netlist using the list of associations is used for generating a hierarchical layout of the electronic components in the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.