John M. Cohn
80Patents
17h-index
122Co-inventors
87Inventor score
Filing activity: Jun 3, 1994 → Oct 5, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7308669B2 | Use of redundant routes to increase the yield and reliability of a VLSI layout | Physics | 192 | Active |
| US7188322B2 | Circuit layout methodology using a shape processing application | Physics | 176 | Expired |
| US5535134A | Object placement aid | Physics | 83 | Expired |
| US6189132A | Design rule correction system and method | Physics | 76 | Expired |
| US7240322B2 | Method of adding fabrication monitors to integrated circuit chips | Electricity | 59 | Expired |
| US6574779B2 | Hierarchical layout method for integrated circuits | Physics | 48 | Expired |
| US5745735A | Localized simulated annealing | Physics | 45 | Expired |
| US6792582B1 | Concurrent logical and physical construction of voltage islands for mixed supply voltage designs | Physics | 42 | Expired |
| US6523154B2 | Method for supply voltage drop analysis during placement phase of chip design | Physics | 34 | Expired |
| US7536664B2 | Physical design system and method | Physics | 32 | Expired |
| US6711719B2 | Method and apparatus for reducing power consumption in VLSI circuit designs | Physics | 27 | Expired |
| US6687883B2 | System and method for inserting leakage reduction control in logic circuits | Emerging Cross-Sectional Technologies | 25 | Expired |
| US6479974B2 | Stacked voltage rails for low-voltage DC distribution | Electricity | 22 | Expired |
| US6473881B1 | Pattern-matching for transistor level netlists | Physics | 21 | Expired |
| US6651230B2 | Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design | Physics | 19 | Expired |
| US6523159B2 | Method for adding decoupling capacitance during integrated circuit design | Physics | 18 | Expired |
| US6832361B2 | System and method for analyzing power distribution using static timing analysis | Physics | 17 | Expired |
| US8565510B2 | Methods for reading a feature pattern from a packaged die | Electricity | 17 | Active |
| US10257270B2 | Autonomous decentralized peer-to-peer telemetry | Electricity | 15 | Active |
| US6430733B1 | Contextual based groundrule compensation method of mask data set generation | Physics | 14 | Expired |
| US6490708B2 | Method of integrated circuit design by selection of noise tolerant gates | Physics | 13 | Expired |
| US7194706B2 | Designing scan chains with specific parameter sensitivities to identify process defects | Electricity | 13 | Expired |
| US6948146B2 | Simplified tiling pattern method | Electricity | 12 | Expired |
| US6751744B1 | Method of integrated circuit design checking using progressive individual network analysis | Physics | 12 | Expired |
| US8187897B2 | Fabricating product chips and die with a feature pattern that contains information relating to the product chip | Electricity | 11 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.