Method and apparatus for logic synthesis (word oriented netlist)
US6574787B1 · kind B1 · utility
41Cited by
9References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Jun 3, 2003 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.