SEQUENCE DESIGN LTD.
28Patents
3Active
28Granted
36Portfolio score
Filing activity: Feb 4, 1999 → Mar 31, 2016 · 1 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6643831B2 | Method and system for extraction of parasitic interconnect impedance including inductance | Physics | 237 | Expired |
| US6591407B1 | Method and apparatus for interconnect-driven optimization of integrated circuit design | Physics | 85 | Expired |
| US6381730B1 | Method and system for extraction of parasitic interconnect impedance including inductance | Physics | 59 | Expired |
| US6698006B1 | Method for balanced-delay clock tree insertion | Physics | 49 | Expired |
| US6574787B1 | Method and apparatus for logic synthesis (word oriented netlist) | Physics | 41 | Expired |
| US6598209B1 | RTL power analysis using gate-level cell power models | Physics | 33 | Expired |
| US6754877B1 | Method for optimal driver selection | Physics | 32 | Expired |
| US6701505B1 | Circuit optimization for minimum path timing violations | Physics | 29 | Expired |
| US6291254A | Methods for determining on-chip interconnect process parameters | Electricity | 29 | Expired |
| US6807660B1 | Vectorless instantaneous current estimation | Physics | 28 | Expired |
| US6701507B1 | Method for determining a zero-skew buffer insertion point | Physics | 25 | Expired |
| US6312963A | Methods for determining on-chip interconnect process parameters | Electricity | 25 | Expired |
| US7222311B2 | Method and apparatus for interconnect-driven optimization of integrated circuit design | Physics | 23 | Expired |
| US6403389B1 | Method for determining on-chip sheet resistivity | Electricity | 23 | Expired |
| US7509613B2 | Design method and architecture for power gate switch placement and interconnection using tapless libraries | Physics | 22 | Active |
| US6519755B1 | Method and apparatus for logic synthesis with elaboration | Physics | 21 | Expired |
| US6701506B1 | Method for match delay buffer insertion | Electricity | 17 | Expired |
| US7323909B2 | Automatic extension of clock gating technique to fine-grained power gating | Electricity | 16 | Expired |
| US7590962B2 | Design method and architecture for power gate switch placement | Electricity | 16 | Expired |
| US6901565B2 | RTL power analysis using gate-level cell power models | Physics | 15 | Expired |
| US7003741B2 | Method for determining load capacitance | Physics | 12 | Expired |
| US7117457B2 | Current scheduling system and method for optimizing multi-threshold CMOS designs | Electricity | 10 | Expired |
| US7222318B2 | Circuit optimization for minimum path timing violations | Physics | 8 | Expired |
| US9103567B2 | Photovoltaic array utilizing phyllotaxic architecture | Emerging Cross-Sectional Technologies | 7 | Active |
| US6493648B1 | Method and apparatus for logic synthesis (inferring complex components) | Physics | 6 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.