Embedded SCR protection device for output and input pad
US6576934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2002 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Oct 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.