Trench MOSFET formed using selective epitaxial growth
US6576954B2 · kind B2 · utility
4Cited by
6References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 6, 2002 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Feb 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.