Chip scale stacking system and method
US6576992B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2001 |
| Grant date | Jun 10, 2003 |
| Priority date | — |
| Expiry date | Oct 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CSPs are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.